1. Field of Invention
The present invention relates to a random access memory. More particularly, the present invention relates to a method of increasing the operating speed of a static random access memory (SRAM).
2. Description of Related Art
Random access memory is a type of volatile memory. There are two major types of volatile memories, namely, static random access memory (SRAM) and dynamic random access memory (DRAM). Digital data is stored as conductive states of the transistor inside a SRAM memory cell. On the other hand, digital data is stored as a charging state of a capacitor inside a DRAM.
Both SRAM and DRAM, however, will lose the stored data once power is cut off FIG. 1 is an equivalent circuit diagram of a conventional SRAM. As shown in FIG. 1, an SRAM has four NMOS transistors 10, 12, 14 and 16, and a pair of loads 18 and 20. The loads 18 and 20 can be resistors, PMOS transistors or depletion NMOS transistors. The NMOS transistors 10 and 12 serve as drivers while the NMOS transistors 14 and 16 serveas SRAM data holders. The gate terminal of both NMOS transistor 14 and 16 is connected to a word line. The drain terminal of the NMOS transistors 14 and 16 is connected to the gate terminal of the NMOS transistors 12 and 10 respectively. Therefore, the switching of the NMOS transistors 10 and 12 and the switching states of the NMOS transistors 14 and 16 are closely related. The source terminals of NMOS transistors 14 and 16 are connected to bit lines BL and BLB. In addition, the substrate terminals of all four NMOS transistors 10, 12, 14 and 16 are connected to an earth voltage terminal.
Since SRAM is a fast-operating memory device, any further increase in executing speed can improve overall operating characteristics of a computer system. However, the substrate terminals of all four NMOS transistors 10, 12, 14 and 16 are connected to an earth voltage terminal, leading to a narrowing of the channel between the source/drain terminals. A narrowed channel restricts current flow during any read/write operation and leads to a considerable drop in performance.
Accordingly, one object of the present invention is to provide a method of increasing the operating speed of SRAM. A voltage is applied to the substrate of component NMOS transistors to increase channel width between the source/drain terminals so that a faster operating speed is obtained during read/write operations while leakage current is lowered during standby.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of increasing the operating speed of a SRAM device. The SRAM is constructed using a plurality of loads and a plurality of NMOS transistors. To read data from the SRAM device, the substrate terminal of the NMOS transistors is connected to a first positive voltage. To write data into the SRAM device, the substrate terminal of the NMOS transistors is connected to a second positive voltage. When the SRAM device is in standby mode, the substrate terminal of the NMOS transistors is connected to an earth voltage.
The range of the first positive voltage and the second positive voltage is smaller than 0.5V. The substrate of the NMOS transistors can be P-type substrate. The loads can be resistors, PMOS transistors or depletion NMOS transistors.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.